Designer, Layout Mask_Tl

Description

The Analog and Memory IP team is searching for key talent to support our mission of providing high quality analog/mixed signal custom layout for our design team and for our internal customers. This mission includes performing custom layout and physical design verification in a large number of different process nodes and PDK’s as needed.

As a layout designer, your responsibilities will include:

Working with our US and CZ based analog designs team or other internal customers to plan, schedule and implement physical designs using process nodes and PDKs from a variety of internal and external foundries Running design verification tools for DRC, ERC, and LVS Implementing ECO to meet design specifications

Qualifications

At least 5+ years of custom analog/mixed signal layout experience Working knowledge of Cadence design & layout tools Working knowledge of DRC/ERC & LVS methods using Calibre toolset Working knowledge in IP and Chip level floorplanning as well as Analog signal flow and matching concerns and can work independently with minimal guidance. Excellent English written and verbal communication skills! Self-motivated with the ability to work independently and interface effectively with team members in remote locations Optional (Plus): BS degree in Electrical Engineering or related field