Designer Sr, Layout Mask_Tl

Description

The Analog and Memory IP team is searching for key talent to support our mission of providing high quality analog/mixed signal custom layout for our design team and for our internal customers. This mission includes performing custom layout and physical design verification in a large number of different process nodes and PDK’s as needed.

As a lead layout designer, your responsibilities will include:

Build and lead a local analog/mixed signal design team Provide managerial oversight to the local layout team, including working with US and CZ teams on planning and execution of tasks, training, and review processes Working with our US and CZ based analog design teams or other internal customers to plan, schedule and implement physical designs using process nodes and PDKs from a variety of internal and external foundries Running design verification tools for DRC, ERC, and LVS Implementing ECO to meet design specifications Mentoring, guiding and training local junior layout talent

Qualifications

At least 10+ years of custom analog/mixed signal layout experience Working knowledge of Cadence design & layout tools Working knowledge of DRC/ERC & LVS methods using Calibre toolset Excellent understanding of IP and chip level floorplanning Excellent understanding of analog IP layout methods to accommodate proper signal flow, matching requirements, density concerns and can work in a highly independent manner Excellent English written and verbal communication skills! Self-motivated with the ability to work independently and interface effectively with team members in remote locations Optional (Plus): BS or MS degree in Electrical Engineering or related field