Physical Design Engineer ( Graduate Trainee)

- plan and execute complex layout efforts covering both high-speed digital and analog designs using state-of-the-art FinFET process technology.
- contribute to the implementation of Intel's custom IP portfolio including the Core fabric, high-speed memory I/O and high-speed SerDes PMA designs.
- assist in specifying and driving user adoption of tool and methodology enhancements aimed at improving layout productivity.

Qualifications

? BS/BEng degree or equivalent
? Strong high-speed digital and/or analog layout experience
? Layout planning and integration skills
? Experience in advanced technology nodes, 20nm and below, including FinFET experience
? Well versed in use of Cadence Virtuoso platform, including SDL
? Experience with Synopsys IC Validator

Inside this Business Group
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

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