This position will work within a team of Chipset Silicon Group which develops USB IP in RTL and associated collaterals for Intel latest chipset and SOC products. The responsibilities will include (but not limited to):- Performs IP level logic design, Register Transfer Level (RTL) coding, and simulation to generate cell libraries and functional units for inclusion in sub-system and downstream SoC or chipset designs.- Participates in the development of Architecture and Microarchitecture specifications for IP.- Advises IP sub-system integration in supporting SoC customers and represents the Soft IP team.**Qualifications**:The applicant should have a bachelor's degree in (Electrical and Electronics or Computer or equivalent) Engineering or higher.- Familiarity or experience in RTL design with Verilog/System Verilog is required.- Familiarity or experience with RTL verification and timing analysis/closure is required is a strong plus.- Knowledge of high-speed serial system interface (such as PCI Express or USB) is a strong plus.- Familiarity with Phyton, Perl, C++ and shell scripts is a plus.- Effective in communication, collaboration and taking initiative.- Motivated to learn and adapt to fast-evolving technologies and environments.**Inside this Business Group**:In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.**Posting Statement**:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.**Benefits**:**Working Model**:This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.**In certain circumstances the work model may change to accommodate business needs.**JobTypeHybrid
