WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ THE ROLE: PCIe SubSystem team delivers industry leading high-performance interconnects IP for all AMD products including dGPU, APU, Server and Game consoles. PCIe IP is one of the most important IP in all AMD's projects. Shanghai PCIe team contributed a lot on the first PCIe Gen4 product and are working on Gen5 product. So, this role provides a great opportunity for working on the most advanced PCIe technology with the global team Architects/Designers/DV on PCIe SS IP Verification. THE PERSON: People who have the passion to work on leading edge technology, who have good communication skills will be preferred in this role. KEY RESPONSIBILITIES: Develop and update infrastructure and environment for IP level design verification. Closely working with Design and Architecture team to develop new verification component Responsible for PCIe SS IP new features verification plan and verification closure PREFERRED EXPERIENCE: Solid background with ASIC design verification flow and multiple ASIC tape out experience with 8+ years Team leading experience and experienced on testbench architecture. Solid knowledge on UVM, SystemVerilog , Verilog is a must Solid background on PCIe is preferred, other high speed IO protocol or Serdes PHY is also a big plus Low power verification work experience is a plus. Knowledge on formal verification is a plus. Fluent written English for technical discussion among global team, vocal is a plus ACADEMIC CREDENTIALS: Candidate is preferred to be MSEE with 8+ years, or BSEE with 10+ years' experience in digital ASIC/SOC design verification. LOCATION: Penang, Malaysia #LI-HS #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.THE ROLE: PCIe SubSystem team delivers industry leading high-performance interconnects IP for all AMD products including dGPU, APU, Server and Game consoles. PCIe IP is one of the most important IP in all AMD's projects. Shanghai PCIe team contributed a lot on the first PCIe Gen4 product and are working on Gen5 product. So, this role provides a great opportunity for working on the most advanced PCIe technology with the global team Architects/Designers/DV on PCIe SS IP Verification. THE PERSON: People who have the passion to work on leading edge technology, who have good communication skills will be preferred in this role. KEY RESPONSIBILITIES: Develop and update infrastructure and environment for IP level design verification. Closely working with Design and Architecture team to develop new verification component Responsible for PCIe SS IP new features verification plan and verification closure PREFERRED EXPERIENCE: Solid background with ASIC design verification flow and multiple ASIC tape out experience with 8+ years Team leading experience and experienced on testbench architecture. Solid knowledge on UVM, SystemVerilog , Verilog is a must Solid background on PCIe is preferred, other high speed IO protocol or Serdes PHY is also a big plus Low power verification work experience is a plus. Knowledge on formal verification is a plus. Fluent written English for technical discussion among global team, vocal is a plus ACADEMIC CREDENTIALS: Candidate is preferred to be MSEE with 8+ years, or BSEE with 10+ years' experience in digital ASIC/SOC design verification. LOCATION: Penang, Malaysia #LI-HS #LI-HybridBenefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
